View BR24T04FVM-WTR_8453993.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

serial eeprom s eries standard eeprom i 2 c bus eeprom (2 -wire) br24t 04 -w general description br24 t 04 - w is a serial eeprom of i 2 c bus interface method features ? completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock ( scl) and serial data ( sda) ? other devices than eeprom can be connected to the same port, saving microcontroller port ? 1.6 v to 5.5v single power source action most suitable for battery use ? 1. 6v to 5.5v wide limit of action voltage, possible fa st mode 400 k hz action ? page write mode useful for initial value write at factory shipment ? self- timed programming cycle ? low current c onsumption ? prevention of write mistake ? write ( write protect) function added ? prevention of write mistake at low voltage ? more than 1 million write cycles ? more than 40 years data retention ? noise filter b uilt in scl / sda t erminal ? initial delivery s tate ffh packages w( typ ) x d( typ ) x h( max ) br24t04 -w capacity bit f ormat type power s ource voltage package 4kbit 512 8 b r24t04 -w 1.6v to 5.5v dip - t8 b r24t04 f-w sop8 b r24t04 fj -w sop - j8 b r24t04 fv -w ssop - b8 b r24t04 fvt-w tssop - b8 b r24t04 fvj-w tssop - b8 j b r24t04 fvm-w msop8 b r24t04 nu x-w vson008x2030 figure 1. sop8 5.00mm x 6.20mm x 1.71mm sop - j8 4.90mm x 6.00mm x 1.65mm vson008x2030 2.00mm x 3.00mm x 0.60mm tssop- b8 3.00mm x 6.40mm x 1.20mm dip - t8 9.30mm x 6.50mm x 7 .10mm tssop- b8j 3.00mm x 4.90mm x 1.10mm msop8 2.90mm x 4.00mm x 0.90mm ssop- b8 3.00mm x 6.40mm x 1.35mm product structure silicon monolithic integrated circuit this product has no designed protection against radioactive rays 1/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 14 ? 001 www .rohm.com datashee t downloaded from: http:///
data s heet br24t04 -w absolute m aximum r atings (ta =2 5c ) parameter symbol rating unit remark supply voltage v cc -0 .3 to + 6.5 v power dissipation pd 450 (sop8) mw derate by 4.5mw/c when operating above ta=25c 450 (sop- j8) derate by 4.5mw/c when operating above ta=25c 300 (ssop -b8) derate by 3.0mw/c when operating above ta=25c 330 (tssop -b8) derate by 3.3mw/c when operating above ta=25c 310 (tssop -b8j) derate by 3.1mw/c when operating above ta=25c 310 (msop8) derate by 3.1mw/c when operating above ta=25c 300 (vson008x2030) derate by 3.0mw/c when operating above ta=25c 800 (dip - t8) derate by 8.0mw/c when operating above ta=25c storage temperature ts t g -65 to + 15 0 c operating temperature topr -40 to +85 c input v oltage/ o utput v oltage \ - 0.3 to vcc+ 1.0 v the max value of i nput voltage / output voltage is not over 6.5v . when the pulse width is 50ns or less, the min value of i nput voltage / output voltage is not lower than - 0.8 v. junction t emperature t jmax 150 c junction temper ature at the storage condition electrostatic discharge voltage (human body model) v esd - 4000 to +4000 memory c ell c haracteristics ( ta=25 c , vcc=1.6v to 5.5v) parameter limit unit min typ max write cycles (1) 1,000,000 times data retention ( 1) 40 years (1) not 100% tested recommended o perating ratings parameter symbol rating unit power source voltage vcc 1.6 to 5.5 v input voltage v in 0 to vcc dc c haracteristics ( unless otherwise specified, ta =- 40c to +8 5c , v cc = 1.6v to 5.5v ) parameter symbol limit unit conditions min typ max input high v oltage1 v ih1 0.7vcc vcc+1.0 v 1.7v Q vcc Q 5.5 v input low v oltage1 v il1 - 0.3 (2) + 0.3vcc v 1.7v Q vcc Q 5.5 v input high v oltage2 v ih 2 0. 8 vcc vcc+1.0 v 1.6v Q vcc 1.7 v input low v oltage2 v il 2 - 0.3 (2) + 0.2vcc v 1.6v Q vcc 1.7 v output low v oltage1 v ol1 0.4 v i ol = 3.0 ma , 2.5v Q vcc Q 5.5v (sda) output low v oltage2 v ol2 0.2 v i ol = 0.7 ma , 1.6 v Q vcc 2 .5v (sda) input leakage current i li -1 +1 a v in =0 to vcc output leakage current i lo -1 +1 a v out =0 to vcc (sda) supply current (write) i cc1 2.0 ma vcc= 5 .5v, f scl = 400k hz, t wr = 5ms , byte write, page write supply current (read) i cc2 0.5 ma vcc=5 .5 v, f scl = 400k hz random read, current read, sequential read standby current i sb 2.0 a vcc=5.5v , sda ? scl=vcc a0,a1,a2=gnd,wp=gnd (2) when the pulse width is 50ns or less, it is - 0.8 v. 2/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w ac c haracteristics (unless otherwise specified, ta =- 40c to +8 5c , v cc = 1.6v to 5.5v) parameter symbol limit unit min typ max clock frequency f scl 400 khz data clock high period t high 0.6 s data clock low period t low 1.2 s sda , scl(input) rise time (1) t r 1.0 s sda , scl (input) fall time (1) t f1 1.0 s sda (output) fall time (1) t f2 0.3 s start condition hold time t hd:st a 0.6 s start condition setup time t su:sta 0.6 s input data hold time t hd:dat 0 ns input data setup time t su:dat 100 ns output data delay time t pd 0.1 0.9 s output data hold time t dh 0.1 s stop condition setup time t su:sto 0 .6 s bus free time t buf 1.2 s write cycle time t wr 5 ms noise spike width (sda and scl) t i 0.1 s wp hold time t hd:wp 1.0 s wp setup time t su:wp 0.1 s wp high period t high:wp 1.0 s (1) not 100% tested. condition inpu t data level :v il =0.2vcc v ih =0.8vcc input data timing reference level: 0.3vcc/0.7vcc output data timing reference level : 0.3vcc/0.7vcc rise/fall time : Q 20ns serial input / outpu t timing input read at the rise edge of scl data output in sync with the fall of scl figure 2-(a ). serial input / output timing figure 2-(b). start -s top bit timing figure 2-(c). wr ite cycle timing figure 2-(d ). wp timing at write execution figur e 2-(e). w p timing at write cancel 70 % 70 % tsu:sta thd:sta start condition tsu:sto stop condition 30 % 30 % 70 % 70 % d0 ack twr write data (n- th address) start condition stop condition 70 % 70 % data( 1) d0 ack d1 data(n) ack twr 30 % 70 % stop condition thd:wp tsu:wp 30 % 70 % data( 1) d0 d1 ack data(n) ack thigh:wp 70 % 70 % twr 70 % scl sda ( ) sda ( ) tr tf1 thigh tsu:dat tlow thd:dat tdh tpd tbuf thd:sta 70% 30% 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 30% tf2 (input) (output) 3/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w block diagram figure 3. bloc k diagram pin configuration (top view) pin description s terminal name input/ output descriptions a0 don t use (1) a1 input slave address setting (2) a2 input slave address setting (2) gnd reference voltage of all input / output, 0v sda input/ output serial data input serial data output scl input serial clock input wp input write protect terminal vcc connect the power source. (1) pins not used as device addr ess may be set to any of h, 'l', and 'hi - z'. (2) a1 and a2 are not allowed to use as open. 9 bit 1kbit~ 256 kbit eeprom array 8 7 6 5 4 3 2 1 sda scl wp v cc g nd a2 a1 a0 address decoder word address register data register control circuit high voltage generating circuit power source voltage detection 8bit ack start stop 4k bit eeprom array 2 5 6 v cc scl gnd br 24t04 -w 1 3 4 7 8 wp sda a2 a1 a0 4/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 6. o utput low voltage1 vs output low current (vcc=2. 5v ) figure 7. output low volta ge2 vs output low current (vcc=1.6v) figure 5. input low voltage1 ,2 vs supply voltage ( a1, a2, s cl, sda, wp) figure 4. input high voltage1 ,2 vs supply voltage ( a1, a2, scl, sda, wp) typical performance curves 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage: vcc(v) input high voltage: v ih1 (v) ta=-40 ta= 25 ta= 85 spec 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 output low current: i ol (m a) output low voltage1: v ol1 (v) spec ta=-40 ta= 25 ta= 85 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 output low current: i ol (m a) output low voltage2: v ol2 (v) ta=-40 ta= 25 ta= 85 spec 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage: vcc(v) input low voltage: v il1 (v) ta=-40 ta= 25 ta= 85 spec 5/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 1 1. supply current (read) vs supply voltage (f scl =400khz) figure 8. input leakage current vs supply voltage ( a1, a2, scl, wp) figure 9. output l eakage current vs supply voltage (sda) figure 10 . supply current (write) vs supply voltage (f scl =400khz) typical performance curves \ continued 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) input leakage current: i li (a) ta=-40 ta= 25 ta= 85 spec 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) output leakage current: i lo (a) ta=-40 ta= 25 ta= 85 spec 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6 supply voltage: vcc(v) supply current (write): icc1(ma) ta=-40 ta= 25 ta= 85 spec 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) supply current (read): icc2(ma) spec ta=-40 ta= 25 ta= 85 6/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 1 3. c lock frequency vs supply voltage figure 1 4. data c lock high period vs supply voltage figure 12. st andby current vs supply voltage figure 1 5. data clock low period vs supply vol tage typical performance curves \ continued 0.1 1 10 100 1000 10000 0 1 2 3 4 5 6 supply voltage: vcc(v) clock frequency: fscl(khz) spec ta=-40 ta= 25 ta= 85 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6 supply voltage: vcc(v) standby current: i sb (a) spec ta=-40 ta= 25 ta= 85 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 supply voltage: vcc(v) data clock high period : t high (s) spec ta=-40 ta= 25 ta= 85 0 0.3 0.6 0.9 1.2 1.5 0 1 2 3 4 5 6 supply voltage: vcc(v) data clock low period : t low (s) spec ta=-40 ta= 25 ta= 85 7/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 1 7. s tart condition setup time vs supply voltage figure 1 8. inp ut data hold time vs supply voltage (high) figure 1 6. s tart condition hold time vs supply voltage figure 19. inp ut data hold time vs supply voltage (low) typical performance curves \ continued 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 supply voltage: vcc(v) start condition hold time: t hd:sta (s) spec ta=-40 ta= 25 ta= 85 -0.2 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 supply voltage: vcc(v) start condition setup time: t su:sta (s) spec ta=-40 ta= 25 ta= 85 -200 -150 -100 -50 0 50 0 1 2 3 4 5 6 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec ta=-40 ta= 25 ta= 85 -200 -150 -100 -50 0 50 0 1 2 3 4 5 6 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec ta=-40 ta= 25 ta= 85 8/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 2 3. h o utput data delay time vs supply voltage figure 2 1. in put data setup time vs supply voltage (low) figure 2 2. l output data del ay time vs supply voltage figure 2 0. in put data setup time vs supply voltage (high) typical performance curves \ continued -200 -100 0 100 200 300 0 1 2 3 4 5 6 supply voltage: vcc(v) input data setup time: t su:dat (ns) spec ta=-40 ta= 25 ta= 85 -200 -100 0 100 200 300 0 1 2 3 4 5 6 supply voltage: vcc(v) input data setup time: t su:dat (ns) spec ta=-40 ta= 25 ta= 85 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) l output data delay time: t pd (s) spec spec ta=-40 ta= 25 ta= 85 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) h output data delay time: t pd (s) spec spec ta=-40 ta= 25 ta= 85 9/ 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 2 4. stop condition setup time vs supply voltage fig ure 2 7. noise spike width vs supply voltage (scl h) figure 2 5. bus free time vs supply voltage figure 2 6. write cycle time vs supply voltage typical performance curves \ continued -0.5 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) stop condition setup time: t su:sto (s) spec ta=-40 ta= 25 ta= 85 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) bus free time : t buf (s) spec ta=-40 ta= 25 ta= 85 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage: vcc(v) write cycle time: t wr (ms) ta=-40 ta= 25 ta= 85 spec 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width(scl h):ti(s) spec ta=-40 ta= 25 ta= 85 10 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 29. n oise spi ke width vs supply voltage (sda h) figure 3 0. no ise spike width vs supply voltage (sda l) figure 3 1. w p hold time vs supply voltage figure 2 8. nois e spike width vs supply voltage (scl l) typical performance curves \ continued 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width(scl l): ti(s) spec ta=-40 ta= 25 ta= 85 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width(sda l): ti(s) spec ta=-40 ta= 25 ta= 85 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) wp hold time: t hd:wp (s) spec ta=-40 ta= 25 ta= 85 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width(sda h): ti(s) spec ta=-40 ta= 25 ta= 85 11 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w figure 3 2. wp setup time vs supply voltage figure 3 3. wp high period vs supply voltage typical performance curves \ continued -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0 1 2 3 4 5 6 supply voltage: vcc(v) wp setup time: t su:wp (s) spec ta=-40 ta= 25 ta= 85 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) wp high period: t high:wp ( s) spec ta=-40 ta= 25 ta= 85 12 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w timing chart 1. i 2 c bus data communication i 2 c bus data communication starts by start condition input, and ends by stop condition in put. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus data communication with several devices is possible by connect ing with 2 communication lines : serial data (sda) and serial clock (scl). among the devices, there should be a master that generates clock and control communication start and end . the rest become slave which are controlled by an address peculiar to each device , like this eeprom. t he device that outputs data to the bus during data comm unication is called transmitter , and the device that receives data is called receiver . 2. start condition (start bit recognition ) (1) before executing each command, start condition (start bit) where sda goes from ' high ' down to ' low ' when scl is ' high ' is necessary. (2) this ic always detects whether sda and scl are in start condition (start bit) or not, t herefore, unless this con dition is satisfied, any command cannot be executed. 3. stop condition ( stop bit reco gnition ) (1) each command can be ended by a stop condition (stop bit) where sda goes from ' low ' to ' high ' while scl is ' high '. 4. acknowledge (ack) signal (1) th e acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in a master - slave communication , the device ( ex. - com sends slave address input for write or read command, to this ic ) at the transmitter (sending) side releases the b u s after output of 8bit data . (2) t he device ( ex. t his ic receives the slave address input for write or read command from the - com) at the receiver (receiving) side sets sda ' low ' during the 9 th clock cycle, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data . (3) this ic, after recognizing start condition and slave address (8bit), outputs ackn owledge signal (ack signal) ' low '. (4) after receiving 8bit data (word address and write data) during each write operation , this ic outputs ackn owledge signal (ack signal) ' low '. (5) during read operation , this ic outputs 8bit data (read data) and detects acknowledge signal (ack signal) ' low ' . when acknowledge signal (ack signal) is detected, and stop condition is not sent from the master ( - com) side, this ic continues to output data. when acknowledge signal (ack signal) is not detected, this ic stops data transfer, recognizes stop c o ndition (stop bit), and ends read operation . then this ic becomes ready for another transmission . 5. device addressing (1) s lave address comes after start condition from master . (2) the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to ' 1010 '. (3) next slave addresses (a2 a1 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. (4) the most ins ignific ant bit ( w/r --- read / write ) of slave address is used for designating write or read operation , and is as shown below. setting w/r to 0 ------- write (setting 0 to word address setting of random read) setting w/r to 1 ------- read slave address maximum number of c onnected buses 1 0 1 0 a2 a1 p0 r/ w DD 4 p0 is p age select bit. 8 9 8 9 8 9 s p condition condition ack stop ack data data address start r/w ack 1-7 sda scl 1-7 1-7 figure 34. data transfer timing 13 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w write command 1. w rite cycle (1) arbitrary data can be written to this eeprom. when writ ing only 1 byte, b yte w rite is normally used, and when writ ing continuous data of 2 bytes or more, simultaneous write is possible by p age w rite cycle. the maximum number of bytes is spe cified per device of each capacity. up to 8 arbitrary bytes can be written . (2) during internal write execution, all input commands are ignored, therefore ack is not r eturned . (3) data is written to the address designated by word address (n - th address) (4) by issuing stop bit after 8bit data input, internal write to memory cell starts. (5) when internal write is started, command is not accepted for t wr (5ms at maximum). (6) using page write cycle, writ ing in bulk is done as follows : w hen data of more than 16 bytes is sent, the bytes in excess overwrite the data already sent first . (refer to "internal a ddress i ncrement ") (7) as for page write cycle of br24t04 -w , where 2 or more bytes of data is intended to be written , after the page select bit p0 of slave address is designated arbitrarily, only the value of 4 least significant bits in the address is incremented internally, so that data up to 16 bytes of memory only can be written . in the case br24t 04 - w, 1 page= 16 bytes, but the page write cycle time is 5ms at maximum for 16by te bulk write. it does not stand 5ms at maximum 16byte= 80ms ( max ) 2. internal address increment page write mode (in the case of br24t 04 - w) 3. write protect (wp) terminal write p rotect (wp) function when wp terminal is set at vcc (h level), data rewrite of all addresses is prohibited. w hen i t is set at gnd (l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or gnd, or c ontrol it to h level or l level. do not use it open. in case of using it as rom, it is recommended to connect it to pull up or vcc. at extremely low voltage at power on / off, by setting the wp terminal 'h', write err or can be prevented . a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address data slave address p0 wa 0 d0 a c k sda line a c k a c k figure 3 5. byte write c ycle figure 3 6. page writ e cycle for example, when it is started from address 0eh, then , increment is made as below, 0eh 0fh 00h 01h ??? please take note. 0eh ??? 0e in hexadec imal, therefore, 00001110 becomes a binary number. wa7 wa4 wa3 wa2 wa1 wa0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 increment 0eh significant bit is fixed. no digit up w r i t e s t a r t r / w a c k s t o p word address(n) data(n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1 p0 a1 a2 wa 7 d0 d7 d0 wa 0 14 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w read command 1. read cycle read cycle is when data of eeprom is read. r ead cycle could be random read cycle or current read cycle. random read cycle is a command to read data by designa ting a specific address, and is used generally. current read cycle is a command to read data of internal address register without designating an address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is a vailable where the next address data can be read in succession . (1) in random read cycle, data of designated word address can be read. (2) when the command just before current read cycle is random read cycle, current read cycle ( each including sequential read cycle), data of incremented last read address (n) - th , i.e., data of the (n+1) - th address is output. (3) when ack signal ' low ' after d0 is detected, and stop condition is not sent from master ( - com) side, the next address data can be read in succession. (4) read cy cle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal goes from l to h while scl signal is 'h'. (5) when 'h' is not input to ack signal after d0, sequential read gets in, and the next data is output. therefore, read command cycle cannot be ended. to end read command cycle, be sure to input 'h' to ack signal after d0, and the stop condition where sda goes from l to h while scl signal is 'h'. (6) sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is asserted from l to h while scl signal is 'h'. figure 37. random read cycle figure 38. curr ent read cycle figure 39. se quential read cycle (in the case o f current read cycle) w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 1 0 0 1 p0 a1 a2 wa 7 a0 d0 slave address 1 0 0 1 a1 a2 s t a r t d7 r / w r e a d wa 0 s t a r t s t o p sda line a c k data(n) a c k slave address 1 0 0 1 p0 a1 a2 d0 d7 r / w r e a d r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 1 0 0 1 p0 a1 a2 d0 d7 d0 d7 15 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w software r eset software reset is executed to avoid malfunction after power on and during command input. software reset has several kinds and 3 kinds of them are shown in the figure below. ( refer to figure 40. - (a) , figure 40. -(b) , and figure 40. - (c) .) within the dummy clock input area, the sda bus is released ('h' by pull up) and ack output and read data '0' (both 'l' level) may be output from eeprom . t herefore, if 'h' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices . acknowledge p olling during internal write execution, all input commands are ignored, therefore ack i s not returned . during internal automatic write execution after write cycle input, next command (slave address) is sent. if the first ack signal sends back 'l' , then it means end of write operation , else ' h ' is returned , which means writing is still in progress . by the use of acknowledge polling, next command can be executed without waiting for t wr = 5ms. t o write continuously, w/r = 0, t hen to carry out curr ent read cycle after write, slave address with w/r = 1 is sent . i f ack signal sends back 'l' , and then execute word address input and data output and so forth . 1 2 13 14 scl dummy clock14 s tart2 scl figure 40- (a) . t he case of dummy clock 14 + start+start+ command input start command from start input. 2 1 8 9 dummy clock 9 start figure 40- (b ). the case of start + dummy clock 9 + sta rt + command input start normal command normal command normal command normal comma nd start 9 sda sda scl sd 1 2 3 8 9 7 figure 40- (c) . start9 + command input normal command normal command sda slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data w rite c ommand during internal write, ack = high is returned . after completion of internal write, ack=low is returned , so input next word address and data in succession. t wr t wr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l figure 41. ca se of c ontinuous w rite by a cknowledge p olling 16 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w wp v alid t iming ( w rite c ancel) wp is usually fixed to 'h' or 'l' , but when wp is used to cancel write cycle and so on , observe the following wp valid timing. during write cycle execution, in side cancel valid area, by setting wp= 'h' , write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in d0 of data(in page write cycle, the first byte data) is the cancel invalid area. wp input in this area becomes don't care . the area from the rise of scl to take in d0 to the stop condition input is the cancel valid area. furthermore , after the execution of forced end by wp, the ic enters standby status . command c ancel by s tart c ondition and s top c ondition during command input, by continuously inputting start condition and stop condition, c ommand can be cancelled. (figure 43.) however, with in ack output area and during data read, sda bus may output 'l '. i n this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. w hen command is cancel led by start - stop condition during random read cycle, sequential read cycle, or cur rent read cycle, internal setting address is not determined . t herefore, it is not possible to carry out current read cycle in success ion. t o carry out read cycle in successi on, carry out random read cycle . ? rise of d0 ta k en clock scl d0 ack enlarged view scl sda ack d0 ? rise of sda sda wp wp cancel invalid area wp cance l va lid area data is not written. figure 4 2. w p valid timing slave address d7 d6 d5 d4 d3 d2 d1 d0 data t wr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address figure 4 3. case of c ancel by s tart, s top c ondition during s lave a ddres s i nput scl sda 1 1 0 0 start condition stop condition enlarged view wp cancel invalid area 17 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w i/o p eripheral c ircuit 1. pull -u p res istance of sda terminal sda is nmos open drain, so it requires a pull up resist or . as for this resistance value (r pu ), select an appropriate value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, operating frequency is limited. the smaller the r pu , the larger is the supply current (read) . 2. maximum value of r pu the maximum value of r pu is determined by the following factors. (1) sda rise time to be determined by the capacitance (c bus ) of bus line and r pu of sda should be t r or lower . furthermore, ac timing should be satisfied even when sda rise time is slow . (2) the bus electric potential a to be determined by the input current leak total (i l ) of device connected to bus at output of 'h' to the sda line and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin of 0.2 vcc. v cc i l r pu 0.2 v cc R v ih ex.) v cc =3v i l =10a v ih =0.7 v cc from (2) Q 30 [k] 3. minimum value of r pu the minimum value of r pu is determined by the following factors. (1) when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. (2) v olmax = 0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. v olmax Q v il 0.1 v cc ex.) v cc =3v, v ol =0.4v, i ol =3ma, microcontroller, eeprom v il =0.3vcc from ( 1) R 867 [] and v ol = 0.4 [v] v il = 0.3 3 = 0.9 [v] therefore, the condition (2) is satisfied. 4. pull -u p resistance of scl terminal when scl control is made at the cmos output port, there is no need for a pull up resistor. b ut when there is a tim e where scl becomes 'hi - z', add a pull up resist or . as for the pull up resistor value , one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroll er . figure 44. i/o circuit diagram microcontroller r pu a sda terminal i l i l bus line capacity c bus br24txx r pu Q 0.8vcc v ih i l r pu Q 0.8 3 0.7 3 10 10 -6 r pu R vcc v ol r pu Q i ol vcc v ol i ol r pu R 3 0.4 3 10 3 18 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w cautions on m icrocontroller c onnection 1. r s in i 2 c bus, it is recommended that sda port is of open drain input/output. however, when us ing cmos input / output of tri state to sda port, insert a series resistance r s between the pull up res ist or r pu and the sda terminal of eeprom. this is to control over current that may occur when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. r s also plays the role of protecti ng the sda terminal against surge. therefore, even when sda port is open drain input/output, r s can be used . 2. maximum value of r s the maximum value of r s is determined by the following relations. (1) sda rise time to be determined by the capacitance (c bus ) of bus line and r pu of sda should be t r or lower . furthermore, ac timing should be satisfied even when sda rise time is slow . (2) the bus electric potential a to be determined by r pu and r s the moment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin of 0.1vcc. ex .) v cc =3v v il =0.3v cc v ol =0.4v r pu =20k 3. minimum value of r s the minimum value of r s is determined by over current at bus collision. when over current flows, noises in power source line and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable curr ent in consideration of the impedance of power source line in set and so forth. set the over current to eeprom at 10ma or lower . e x. ) vcc =3v i=1 0 ma (vcc v ol ) r s r pu +r s r pu microcontroller r s eeprom figure 45. i/ o circuit diag ram figure 46. input / output collision timing ack 'l' o utput of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom . scl sda microcontroller eeprom 'l'output r s r pu 'h' output over current i figure 48. i/o ci rcuit diagram figure 47. i/o circuit diagram r pu micro controller r s eeprom i ol a bus line capacity c bus v ol v cc v il +v ol +0.1vcc Q v il r s Q r pu v il v ol 0.1vcc 1.1vcc v il Q 1.67 [k] r s Q 0.3 3 0.4 0.1 3 1.1 3 0.3 3 20 10 3 r s R 3 10 10 3 R 300 [] vcc r s Q i r s R vcc i 19 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w i/o equivalen ce circuit 1. input ( a1, a2, scl, wp) 2. input / output (sda) figure 49. in put pin circuit diagram figure 50. input / outpu t pin circuit diagram 20 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w power - up / down conditions at power on , the ic s internal circuit s may go through unstable low voltage area as the vcc rises , making the ic s internal logic circuit not completely reset, hence, malfunction may occur. to prevent this , the ic is equipped with por circuit and lvcc circuit. to assure the operation , observe the following conditions at po wer on . 1. set sda = 'h' and scl = 'l' or 'h 2. start power source so as to satisfy the recommended conditions of t r , t off , and v bot for operating por circuit. t off t r v bot 0 v cc 3. set sda and scl so as not to become 'hi - z'. when the above conditions 1 and 2 cannot be observed, take the following countermeasures. (1) in the case when the above condition 1 cannot be observed such that sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. (2) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset ( page 16). (3) in the case when the above conditions 1 and 2 cannot be observed. carry out (1 ), and then carry out (2). l ow v oltage m alfunction p revention f unction lvcc circuit prevents data rewrite operation at low power, and prevents write error . at lvcc voltage ( typ = 1.2v) or below, data rewrite is prevented . n oise c ountermeasures 1. bypass capacitor when noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a bypass capacitor (0.1 f) between ic vcc and gnd pins . connect the capacitor as close to ic as possible. in addition , it is also recommended to connect a bypass capacitor between boards vcc and gnd. recommended conditions of t r , t off ,v bot t r t off v bot 10ms or below 10ms or larger 0.3v or below 100ms or below 10ms or larger 0.2v or below figure 5 1. rise waveform diagram figure 5 2. when scl= 'h ' and sda= 'l' figure 5 3. when s cl= 'l ' and sda='l' t low t su:dat t dh after vcc becomes stable scl v cc sda t su:dat after vcc becomes stable 21 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w operational notes 1. descri b ed numeric values and data are design representative values only , and the values are not guaranteed. 2. we believe that the application circuit examples in this document are recommendable. however, in actual use, confirm characteristics further sufficiently. if changing the fixed number of external parts is desired, make your decision with sufficient margin in consideration of static cha racteristics, transient characteristics, and fluctuations of external p arts and our lsi . 3. absolute m aximum r atings if the absolute maximum ratings such as supply voltage, operating temperature range, and so on are exceeded, lsi may be destroyed. do not supply voltage or subject the ic to temperatures exceeding the absolut e maximum ratings. in the case of fear of exceeding the absolute maximum ratings, take physical s afety countermeasures such as adding fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supp lied to the lsi . 4. gnd e lectric p otential set the voltage of gnd terminal lowest at any operating condition. make sure that each terminal voltage is not lower than that of gnd terminal . 5. t hermal d esign use a thermal design that allows for a sufficient margin by taking int o account the permissible power dissipation (pd) in actual operating conditions. 6. short between p ins and m ounting errors be careful when mounting the ic on printed circuit boards. the ic may be damaged if it is mounted in a wrong orientation or if pins are shorted together. short circuit may be caused by conductive p articles caught between the pins . 7. operating the ic in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently . 22 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w part numbering b r 2 4 t 0 4 x x x - w x x bus t ype 24 i 2 c operating temperature / power source volta ge - 40 to+ 85 / 1.6v to 5.5v capacity 04=4k package b lank :dip - t8 f :sop8 fj :sop - j8 fv : ssop -b8 fvt : tssop -b8 fvj : tssop -b8j fvm : msop8 nux : vson008x2030 double cell packaging and forming specification e2 : embossed tape and reel (sop8, sop - j8, ssop -b8,tssop- b8, tssop -b8j) tr : embossed tape and reel (msop8, vson008x2030) none : tube (dip - t8) 23 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w physical dimensions tape and reel information 24 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 25 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 26 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 27 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 28 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 29 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 30 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w 31 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w marking diagrams (top view) dip - t8 (top view) br24t04 -w part number marking lot number sop8 ( top view) part number marking sop - j8 ( top view) part number marking lot number tssop- b8 ( top view) part number marking tssop- b8j ( top view) part number marking lot number 1pin mark ssop- b8 ( top view) part number marking lot number 1pin mark vson008x2030 (top view) part number marking lot number 1pin mark t 0 4 t 0 4 msop8 ( top view) part number marking lot number 1pin mark t 0 4 t 0 4 t 0 4 t 0 4 t 0 4 1pin mark 1pin mark 1p in mark l ot number lot number 32 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
data s heet br24t04 -w re vision history date revision changes 18. may .2012 001 new release 2 5.feb .2013 002 update some english words, sentences descriptions, grammar and formatting. add tf2 i n serial input / output timing 31.may.2013 003 p1 change format of package line - up table. p.2 add vesd in absolute maximum ratings p. 4 add directions in pin descriptions 12.dec.2014 004 p.32 change the marking of ssop - b8 package from 3 rows to 2rows 33 / 33 tsz02201 - 0r2r0g100080 -1-2 12 . dec .201 4 rev.00 4 ? 2013 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com downloaded from: http:///
datasheet d a t a s h e e t notice-ge rev.004 ? 2013 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hms products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class ? class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. if the flow sol dering method is preferred on a surface-mount products, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
datasheet d a t a s h e e t notice-ge rev.004 ? 2013 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohms internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice C we rev.001 ? 2014 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

▲Up To Search▲

Price & Availability of BR24T04FVM-WTR

	To Download BR24T04FVM-WTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .